Daniel Tyukov

Two open-source IP cores, each verified against an independent software model and then hardened far enough to quote real silicon numbers instead of synthesis estimates.

Colour VGA text-mode controller

Per-character foreground and background from a 16-entry palette, a hardware cursor with programmable blink, reverse video and underline, runtime-selectable 8x8 and 8x16 fonts, and three video modes (640x480, 800x600, 1024x768) driven from a VESA timing package, so adding a mode is a table entry. Verification is pixel-exact against a Python renderer, with numeric assertions on porch and sync widths per mode and an underrun test that starves the fetch port and checks the sync outputs stay valid.

The pixel domain closes at 95.96 MHz at the slow corner, so every mode has margin: 1024x768 holds +4.964 ns. Post-route the die is 476,640 μm² (0.477 mm²) at 60.3% utilisation, 10.5 mW at 65 MHz, DRC and LVS clean. That die is 2.72x the synthesis cell-area estimate, a figure most write-ups omit.

CORDIC accelerator

An OBI subordinate interface built as a drop-in user_domain peripheral for the Croc RISC-V SoC. All three coordinate systems (circular, linear, hyperbolic) in both rotation and vectoring modes, with quadrant pre-rotation for full four-quadrant range, the repeated iterations hyperbolic convergence requires, and documented gain handling.

Two microarchitectures sit behind one interface, fully pipelined and folded, so the area against throughput trade is measured rather than asserted: the folded variant routes to 383,154 μm² at 67.7 MHz against a 75.2 MHz synthesis estimate. Accuracy is swept per function against double precision, and an RV32 baremetal driver builds and links with picolibc.

Both repositories are fork-ready, with contributing and adaptation guides.

During my MSc Electrical Engineering at TU Delft, I designed a PCB test vehicle for micro-LED die bonding, joined the cleanroom session that populated it, and ran the electrical characterization that categorized eight assembly conditions. With TU Delft ECTM and ITEC B.V. / Nexperia, extending the v1 board published at ECTC 2025.

Board. 93 × 93 mm, two-layer FR-4, ENIG with all pads gold, carrying every structure needed to characterize a bond on one substrate, so one cleanroom session yields bond resistance, contact resistivity, sheet resistance and junction thermometry from the same hardware. A 6 × 6 bond-pad design of experiments at 3.5 mm pitch crosses three pad geometries with three fillet radii, alongside TLM ladders at 0.25, 0.5 and 1.0 mm width, van der Pauw cloverleaves, 26 Würth WL-SFCC 0404 RGB LEDs, four NTCs for forward-voltage thermometry, and an LCR calibration set. KiCad 9, DRC clean, fab-ready to the Eurocircuits standard pool. The LED pads ship as bare gold, because the joint itself is the research subject and has to form under controlled conditions.

Bonding. Paste printed by hand through a 100 μm stencil, dies placed on a Tresky T-3000-PRO, joint formed on a hot plate with Sn42Bi57.6Ag0.4. When the paste melts, surface tension pulls each die toward the centre of its pad set, but the same forces can tilt a die and lock it there, because tilt is the one non-restoring self-alignment mode for a rectangular chip. Read against the capillary self-alignment literature, the alignment and tilt point to solder volume as the dominant process variable, which manual printing does not meter.

Characterization. Eight blind-coded conditions, five coupons, 120 channels. Round 1 screened every channel on a DMM and called six bad; the sweep rig later agreed on all six and disagreed on none. Round 2 swept 63 current levels per channel on an Arduino rig, fitting the diode equation across 89 sweeps.

Yield and failure mode separate the conditions, at χ² p = 2.2e-4, with two of them at 100 percent. Series resistance does not: re-seating the fixture moves R_s by 0.84 Ω, which is 85 percent of the apparent die-to-die spread, while the bonds being chased are 10 to 100 mΩ. The experiment was never capable of resolving them, and the repeatability study is what proves it, so the limit is reported rather than worked around. The ideality check cost nothing and caught a 2.9 kΩ shunt on a contaminated die that the DMM had passed at 1.781 V.

Two open-silicon designs taken from RTL to a signed-off GDS on IHP’s open-source SG13G2 130 nm process, using the same LibreLane flow the Tiny Tapeout shuttle runs. Both are DRC and LVS clean, and both can be inspected in a browser through a 3D GDS viewer.

VGA pattern engine multiplexed by a hardware TRNG

Six pattern generators derive colour combinationally from pixel position and frame count, because a 1x1 tile has no room for a framebuffer. The entropy path is a ring-oscillator source into von Neumann debiasing, LFSR whitening, and online health tests in the spirit of NIST SP 800-90B. Verification is pixel-exact against an independent Python model of every pattern, plus numeric assertions on the full 800x525 VGA timing rather than a visual check. 25.175 MHz closes at the slow corner (1.08 V, 125 °C) with +0.0989 ns slack, and the post-route die is 31,318 μm² at 82.7% cell density.

Signed-INT8 neural network accelerator

A weight-stationary systolic MAC array with integer-only per-channel requantization: INT32 accumulate, bias, fixed-point multiplier, rounding shift, zero point, saturate. Hand-written parameterized adders (ripple-carry, Brent-Kung, Kogge-Stone, Han-Carlson) and multipliers (Baugh-Wooley, Wallace, Booth radix-4) are formally proved equivalent with SymbiYosys, then compared on measured area and delay.

On scikit-learn digits, INT8 matches float32 exactly at 0.883 accuracy: quantization moves the output layer by up to 1.81 LSB but never beyond the decision margin, so no prediction flips. The 6x2 tile was chosen by hardening 4x2, 6x2 and 8x2 and comparing signoff.

Hardening ran locally and in CI. Shuttle submission and fabrication still require Tiny Tapeout.

An open-source ASIC test chip built to settle two questions by measurement rather than argument: which INT8 matrix-multiply microarchitecture is actually better in silicon, and does sign-magnitude operand encoding really reduce power?

Seven candidates sit behind one identical interface and are selected at runtime, so they are compared under conditions identical by construction: inferred (Yosys and ABC pick the structure), Wallace tree, Booth radix-4, sign-magnitude, bit-serial, plus the array wrapper and benchmark core. An SPI control plane loads operands, triggers compute and reads back results, cycle counts and MAC counts, with an on-chip comparator checking against a loaded golden matrix. Every candidate is verified bit-exact against a NumPy INT32-accumulator reference and cross-checked against the others, so any PPA difference is microarchitectural rather than functional.

Five candidates went through place and route at an identical clock constraint. Post-route, slow signoff corner:

Candidate	Area	Fmax	Power	Energy/op
Booth radix-4	383,415 μm²	83.0 MHz	8.21 mW	419 pJ
Sign-magnitude	394,146 μm²	69.2 MHz	8.41 mW	429 pJ
Inferred	443,933 μm²	81.4 MHz	8.73 mW	446 pJ
Wallace tree	476,959 μm²	77.9 MHz	9.35 mW	477 pJ
Bit-serial	185,463 μm²	77.3 MHz	6.51 mW	1,245 pJ

Two findings worth stating plainly. Booth radix-4 wins on area, frequency, power and energy simultaneously, while the hand-written Wallace tree is the worst single-cycle candidate on three of those axes: letting the synthesiser choose beat hand-structuring here. And the sign-magnitude hypothesis does not hold. It costs 4.2 percent instead of saving power, because the conversion hardware is pure overhead. A cheap switching-activity proxy also ranks the two frontier candidates the wrong way round once real routed energy is measured, so it screens but does not decide.

Full-custom 5-bit time-to-digital converter designed and verified during my MSc Electrical Engineering at TU Delft. The circuit digitizes the time difference between two rising edges with a 15 ps least significant bit, finer than a single inverter delay in the target TSMC 180 nm BCD process.

The design uses a two-dimensional Vernier architecture: two delay lines with stage delays of 90 ps and 75 ps carry the START and STOP edges into a 10x10 grid of NAND-based SR-latch arbiters, so 16 delay stages resolve 31 output codes, cutting the number of delay cells by about 4x compared to a classical 1-D Vernier line. A bijective routing map sends one latch to each thermometer output bit, and the grid is dummy-padded so every delay tap sees identical fan-out, which keeps linearity flat across process corners.

Every transistor was sized by hand in Cadence Virtuoso, with no standard cells. Spectre verification covers all five process corners (TT, SS, FF, SF, FS): the transfer characteristic is monotonic with no missing codes, DNL stays within 1 LSB, and a MOSCAP-based calibration bank tightens the LSB spread across corners from 5.1 ps to 0.85 ps. The SR-latch arbiter was separately characterized for metastability, with a decision dead zone below 1 fs. Energy per conversion is about 11 to 13 pJ.

A personal rebuild of the NASA-IMPACT marine debris detector, finding floating plastic in the ocean from free satellite imagery. The original ran a TensorFlow 1.14 detector on commercial Planet imagery, needed a Planet API key, and no longer installs on current Python. This version keeps the idea and the geo-referencing math and replaces the rest: PyTorch, free Sentinel-2 10 m imagery read over HTTP, one pip install and one CLI command, no training, no GPU and no API keys.

The pipeline is a cascade, because a vision transformer costs about 18 seconds per tile on CPU while a Sentinel-2 scene is 120 megapixels. Spectral arithmetic (FDI, FAI, NDVI, NDWI, PI, kNDVI, MNDWI) screens the scene in microseconds per tile, then OWLv2 open-vocabulary detection and SAM 2 segmentation only run where something looks interesting. On a coastal scene off Accra that avoided 44% of detector calls, cutting 11.1 minutes to 6.2. On three open-ocean MARIDA test scenes it reached precision 1.00 at about 0.71 recall with zero false positives.

I also trained a supervised baseline on MARIDA, the public Sentinel-2 benchmark, on its scene-grouped split so no test scene leaks into training: gradient boosting over 18 per-pixel features and 624,000 labelled pixels, 76 seconds to fit on CPU, reaching precision 0.944 at recall 0.354.

The most interesting result is a negative one. The same OWLv2 weights score 0.794 confidence on a COCO photograph and 0.210 on a Sentinel-2 chip: at 10 m resolution a 30 m debris patch spans three pixels, so a photographic prior has nothing to key on. The physics carries the signal, not the vision model, and feature importance agrees: B05 (red edge) and B01 (coastal aerosol) outrank every named index. The detector still earns its place by labelling the ships, wakes and foam a one-class model would call debris. 761 tests run in CI.

A nine-person hardware team, powering a desktop PC wirelessly from a sustainable source across a 10 to 20 cm air gap at 100 W or more, with maximum power point tracking.

Six blocks in series: a generator, a DC/DC boost converter, a full-bridge DC/AC inverter, two resonant magnetically coupled coils, an AC/DC rectifier and the load, coordinated by a microcontroller that measures voltage and current at every stage and sets the PWM duty cycle and switching frequency.

The boost converter takes the generator’s rectified DC, up to 30 V and limited to 10 A, and holds a regulated 50 V for the rest of the chain. It switches an IRF640N at 20 kHz through an EL7104 gate driver, with an MBR10100+ Schottky, a 75 to 125 μH inductor sized for continuous conduction and a 220 μF output capacitor, holding 49 V at 4.95% ripple against a 5% limit. The inverter chops that rail with four IRF640N switches and two IR2110 half-bridge drivers into 40 to 50 kHz AC for the transmit coil. Both boards were laid out in KiCad with continuous ground planes, current-scaled trace widths and placement chosen to spread heat and limit EMI, then fabricated from our own gerbers.

Sensing sits on the boards: LA 55-P Hall-effect transducers and 21:1 dividers bring current and voltage at each conversion stage to the STM32 firmware that runs the PWM and the MPPT search. We modelled the chain in MATLAB and Simulink first, then brought the hardware up from low voltage against breadboard references.

The integrated system reached 77.36% peak efficiency at 180.80 W output, past the 100 W target. MPPT and automatic load detection were designed but not fully brought up in hardware.

My five-person team accelerated and hardened AES-128 encryption on a CV32E40P (RISCY) RISC-V soft core running on a PYNQ-Z1 (Zynq-7000) FPGA, combining RTL, LLVM compiler, and side-channel work. We drove the workload from 61,184 cycles down to 4,104 cycles, about 15x fewer, while adding first-order side-channel resistance. All cycle counts were measured directly from the hardware cycle counter in Vivado XSim and verified against the AES-128 known-answer test.

Profiling showed one function, mix_columns, burning 83.8% of all cycles, which motivated the hardware work. We implemented the RISC-V scalar-cryptography (Zkne) instructions aes32esmi and aes32esi in the CV32E40P ALU and decoder, each fusing a full round step into a single-cycle instruction. That alone cut the workload to 6,260 cycles (9.8x). A custom loadable LLVM pass then fully unrolled the 9-round AES loop, removing per-round branch and pointer overhead the -Os optimizer refused to touch, reaching 4,800 cycles with identical ciphertext.

My individual track was side-channel resilience: I designed a 2-share Domain-Oriented-Masking tower-field S-box in GF((2⁴)²) with 20 bits of fresh randomness per evaluation, and built a simulation-based CPA and TVLA attack rig. A textbook attack recovered the key in about 100 traces before masking; after, it failed within 20,000 traces, cutting the leakage t-statistic from 44 to 1.4. Everything stayed within the FPGA timing budget at 100 MHz.

Fabricated and characterized NMOS and PMOS transistors in the BICMOS5 process at the Else Kooi Laboratory (EKL) cleanroom, following the devices through every stage from theory to measurement.

• Theory: hand calculations for Deal-Grove oxidation, implantation range and straggle, and junction depths.
• Simulation: Sentaurus TCAD process and device simulations across the four dopants in the flow (P, As, B, Sb), producing implant, diffusion and masking profiles, NMOS and PMOS cross-sections, and full ID-VG and ID-VDS families with threshold voltage against implant dose.
• Processing: a 2.5 day cleanroom session on partially processed wafers with four-point-probe sheet-resistance mapping, ellipsometer oxide-thickness measurements before and after BHF etching, and wet against dry etch selectivity under the microscope.
• Measurement: process-control-module characterization on a Cascade probe station with a Keysight B1500A, extracting sheet resistance and doping from Van der Pauw structures, lateral out-diffusion from ELM resistors, and threshold voltage, mobility and short-channel effects across transistor geometries, all re-analyzed in a single MATLAB pipeline that regenerates every figure.

Key results: NMOS +0.82 V and PMOS −3.30 V threshold at the highest VT-adjust dose with monotonic VT against dose matching simulation, long-channel mobilities of about 750 (electron) and 240 (hole) cm²/Vs, and sheet resistances from 0.16 Ω/sq (metal) to 1740 Ω/sq (n-well), cross-checked against the class consensus with fit R² above 0.99 throughout.

Accelerated the de Gruijl Inferior-Olive neuron-network simulator, a sequential Python model of coupled brain cells, on CPU and GPU. Starting from the reference simulator, I built a single vectorised simulation step with three interchangeable backends: NumPy, Numba (@njit), and JAX (jit plus lax.scan) running on both CPU and an NVIDIA T4 GPU.

The main algorithmic win was the gap-junction coupling. The original all-to-all interaction between cells is O(N²); I reformulated it as an O(N) mean-field term C_gap·(N·V_d − Σ V_d), which removed the dominant bottleneck and let the simulator scale to large populations.

I profiled the baseline with cProfile, then timed every backend over network sizes from N = 1 to 100,000 cells, reporting microseconds per simulation step. Numerical fidelity was validated carefully: at N = 1 (no coupling) every backend matches the reference simulator to about 1e-14 mV. For N > 1 the only difference is moving the gap junction from an in-step Gauss-Seidel sweep to a Jacobi update, which stays within 0.02 mV (correlation 1.0000 at N = 30). I also characterised numerical stability, showing forward-Euler holds only for N < 2/(δ·C_gap) = 4000 at the fixed coupling strength, and explored the network dynamics (soma-trace amplitude, spike count, dominant frequency, population synchrony).

Designed and modeled an electrostatic comb-drive MEMS optical phase shifter, the actuator behind an integrated optical phase modulator of the kind used in photonic quantum circuits. A bias voltage pulls a suspended silicon shuttle toward the comb electrodes, moving a modulation bar over a 200 nm gap above an optical waveguide and shifting the phase of the light passing through.

I took the device through three escalating modeling stages, each validating the last. First, an analytical lumped spring-mass-damper model, derived by hand and reproduced in MATLAB, set the dynamics and limits: 40.3 N/m stiffness, 537 kHz resonance, Q of 81, 145 μs settling, and finger-tip pull-in near 347 V. Second, a 2D finite-element model in COMSOL, coupling solid mechanics, electrostatics, and a moving mesh, confirmed the lumped dynamics within 9% and showed that pull-in is a symmetry-breaking side instability at 224 V rather than the axial mode. Third, I reduced the phase sensitivity to a closed-form objective and ran a constrained grid search over roughly 10⁶ candidate designs across the real technology window, then re-validated the winner in COMSOL. The optimized design places its sensitivity peak safely below pull-in, raising achievable phase sensitivity from about 8.7 to 73.9 mrad/V, an 8.5x gain at a stable operating point. A full 3D model confirmed the in-plane working mode survives out of plane.

The entire finite-element workflow is script-driven through the MPh Python API, so every number and figure regenerates end-to-end from source.

Designed hardware FFT accelerators for a PicoRV32 RISC-V system-on-chip and took them through the complete ASIC flow: RTL design, constraints, logic synthesis in Cadence Genus, place-and-route in Cadence Innovus, signoff, post-layout simulation and power analysis on a 45 nm process (gpdk045), in a team of eight. Two tape-out-ready designs were delivered against the same SoC and an unmodifiable testbench.

• High-Performance: register-file operand storage feeding a four-phase pipelined butterfly at 66.2 MHz. Latency drops about 33x against the 12 MHz iterative baseline (61.0 to 1.83 μs) while total energy still falls 4.8x to 5.1 nJ.
• Energy-Efficient: real-input packing into a 16-point FFT computed as two Radix-4 stages (the first multiplier-free) with Hermitian recombination and manual integrated clock gating. At the unchanged 12 MHz clock, energy per transform drops 9.5x to 2.59 nJ at 0.239 mW.

Both designs close signoff cleanly: zero setup and hold violations post-route and clean DRV, connectivity and antenna checks. Everything is verified end to end with behavioural, post-synthesis and post-layout (SDF back-annotated) simulation plus VCD-annotated power analysis. My personal focus was the full-flow bring-up, baseline characterization, signoff, cross-branch design reviews, and the report.

Designed a discrete-time, fully differential folded-cascode operational amplifier with gain boosting on a 180 nm CMOS process, sized for the lowest possible power. The amplifier sits in a switched-capacitor feedback network (18 pF input, 2.25 pF feedback, 18 pF load) and must settle a 1.2 V differential output step to 63 dB accuracy within 2.8 μs.

The full testbench included the bias generator, ideal common-mode feedback, ideal gain-boosting sources for the PMOS and NMOS cascodes, and both loaded and unloaded amplifier instances, so that open-loop, closed-loop, transient, and noise runs shared one operating point. Designed and verified in LTspice, extracting each deliverable from the AC, transient, and noise decks.

The result met or beat every target: settling accuracy of 63.32 dB and settling time of 2.8 μs at 0.112 mW, an SNR of 80.85 dB against an 80.64 dB target, and total integrated output noise of 76.9 μVrms. The figure of merit reached 175.2 dB against a 174.0 dB target. Closed-loop bandwidth from the open-loop and closed-loop AC runs agreed at 329 kHz, and the transient time constant (497 ns) matched the AC prediction (483 ns) within 3 percent.

Designed the first amplifier stage of a hearing-loop receiver, the block that converts a pickup coil’s magnetic signal into a clean audio voltage for the following analog-to-digital converter. Because the coil output is proportional to the rate of change of magnetic flux, the amplifier had to act as an integrator to keep the audio band flat while driving a 10 pF converter input on a 1 mW power budget.

I followed a top-down structured design method: fix the specification and the target transfer, then build the circuit block by block as an ideal noisy nullor before committing to transistors. Noise budgeting set the input device. A single common-source stage could not hold enough loop gain across the band, so I moved to a two-stage topology, a low-noise PMOS differential input pair followed by a high-gain NMOS common-source output, reaching about 45 dB of loop gain. The realized amplifier covers a 600 Hz to 6 kHz passband with roughly 7.5 μVrms weighted output noise, below the 10.6 μV budget and under the microphone noise floor.

Pole-zero analysis on the EKV transistor model placed all five poles in the left half-plane, but one pair peaked at Q of about 5.4. A single phantom-zero resistor near 0.42 kΩ pulled that pair to Q of about 0.70 for a maximally flat response, with no compensation capacitor and no added signal-path noise.

Developed and characterized a simplified gold-bump flip-chip bonding process for RF integrated circuits during my BSc Electrical Engineering (Integrated Circuits group). The process replaces complex multilayer metal stacks and solder-based assembly with a single-layer 50 nm Ti / 100 nm Au ground-signal-ground coplanar waveguide interposer on a low-cost glass substrate plus 70 μm thermosonic gold stud bumps, so the whole flow runs on standard university cleanroom equipment.

Designed the 50 Ω GSG interposer masks in KLayout, fabricated the interposers in the TU/e cleanroom, formed the gold stud bumps with a thermosonic wire bonder and assembled the dies by thermo-compression flip-chip bonding on a Dr. Tresky T-5300. A statistical yield analysis confirmed high interconnect yield with damage-free assembly of thin RF dies. Characterized the assemblies from 10 MHz to 10 GHz with a vector network analyzer and GSG probes, built a de-embedding methodology, and extracted lumped RLC models for the gold bumps and a pi-model for the transmission lines in QUCS. The measured characteristic impedance of 49.8 Ω matches the 50 Ω design target, and the validated models are ready for process design kit integration.

Written up as a first-author conference paper (SIITME 2025), published on IEEE Xplore.

LeenLoket (“lending desk” in Dutch) is a self-service tool library. Instead of buying a drill you use twice a year, you book one from your phone for a date range, walk to the locker it lives in, and open that locker with a PIN or a QR code. Two repositories: the Flutter app and the ESP32 locker firmware.

There is no backend of our own. The app and the firmware are both Firebase Realtime Database clients, and that database is the entire integration surface between them. Nine top-level nodes hold users, items, reservations, codes, credit and locations. Either half can be replaced without the other knowing.

The app does email and password auth over Rive-animated onboarding, a date-range picker that filters the catalogue to items free for that window, a two-step booking flow priced at pricePerDay times days and paid from a prepaid balance, reservations each carrying a 4-digit PIN and a QR code, and a Google Map of locker locations. Admins land on a separate home screen with CRUD for items, categories, lockers and locations, plus credit top-ups.

The locker is an ESP32 driving a 4x4 keypad, an I2C QR reader, a PN532 NFC reader, an ST7920 LCD and eight WS2812B LEDs, plus a solenoid lock wired fail-secure so a power cut leaves the cabinet shut.

The rule that makes it work: there is no “I am returning this” button. The firmware tells a pickup from a return by reading two fields, the reservation status and the item status, so the same four digits work twice. The first use flips the reservation to Completed, which is what makes the second read act as a return. A late pickup is the only path that does not open the door. A late return still opens, because refusing to accept an item back helps nobody.

Both READMEs list what the deadline left broken, including a return loop that spins forever waiting for the NFC tag.

An individual analog design project. The goal was a sine wave oscillator running at 10 kHz with an output amplitude adjustable from 0 to 5 Vpp and low harmonic distortion.

I compared three oscillator architectures (RC phase-shift, LC, and Wien bridge) on frequency stability, waveform purity, and complexity, then chose a Wien bridge for its clean sine output and simple frequency setting. The RC frequency-selective network sets the 10 kHz oscillation point using matched 10 nF capacitors with resistors near 1.2 kΩ. One op-amp provides the loop gain, a second stage gives the adjustable output amplitude, and a diode pair stabilizes the amplitude so the loop settles just above the oscillation condition instead of clipping. To cut harmonic content I added a filter stage, the main innovation of the design.

Built and simulated in Qucs, then realized on a breadboard and measured with a LabVIEW-based bench instrument. The final prototype produced a clean sine at 10.04 kHz and 5.019 Vpp with a measured total harmonic distortion of 0.96 percent.

Pulse is a bicycle navigation device that guides riders through haptic feedback instead of a screen, so cyclists can keep their eyes on the road. Built with a five-person team spanning electrical engineering, computer science, mechanical engineering, and industrial design.

The system has two parts that talk over Bluetooth Low Energy. An Android app runs a notification listener that reads the Google Maps navigation notification, extracts the distance to the next turn and the maneuver icon, and classifies the maneuver by matching the icon bitmap against a library of known direction samples. It packs the result into a short code such as r:120, meaning turn right in 120 meters, and writes it to a BLE characteristic on the handlebar unit.

The handlebar device is an Arduino Nano ESP32 running a NimBLE GATT server, wired to two vibration motors and a status LED and powered by a LiPo battery. The direction code selects which side buzzes and the pattern, while the distance sets the buzz timing so the cue grows more urgent as the turn approaches. The electronics sit in a 3D-printed enclosure that clamps to the handlebar.

Sputnik-15 is an autonomous exploration rover built for a simulated Venus surface as a team project. On a walled arena the rover has to drive around on its own, find rock samples, pick them up, avoid the mountains and arena edges, then locate a laboratory and drop the samples off before repeating. Everything runs on a single Arduino Uno with no remote control.

The control loop is a function-based state machine in C++ (PlatformIO). A Parallax PING ultrasonic sensor on a servo sweeps a 105 degree arc ahead and converts echo time to distance to detect obstacles; when something is too close the rover backs up and turns away. Five downward-facing infrared sensors read the floor: the outer pair catch the arena border and ramp edges, while the front sensors detect rock samples. A servo gripper closes on a sample once one is found. The laboratory is marked by a 38 kHz infrared beacon; the rover carries a matched IR receiver, so once it holds a sample it rotates until the beacon is in sight, drives toward the lab, and releases. The strategy is organized as a loop over four phases: explore, collect, locate and deliver.

The team also prototyped a camera-based approach using a Raspberry Pi with OpenCV and ArUco markers, kept as an optional extra since it fell outside the assignment rules.

A robotic cradle that soothes a crying baby on its own. A baby simulator in the cradle expresses stress through two signals, crying sound and heart rate. The system senses both, rocks the cradle with a motor, and searches for the motion that calms the baby fastest. In the course competition our algorithm won the Fastest Algorithm category with a time of 01:42.

The build is split across four sub-modules, each running on its own M5Stack (ESP32) and tied together by a custom backbone interface board. A microphone measures crying loudness by counting signal peaks per second with a rising-edge interrupt and comparing consecutive one-second windows. A light-dependent resistor reads a pulsing LED standing in for the heartbeat and converts the interval between light changes to beats per minute. A PWM motor driver rocks the cradle using two parameters, frequency and amplitude, each with five discrete levels from 5 to 80 percent duty cycle.

At the core is an inverse-model decision algorithm that treats the rocking as a point in a 2D frequency-amplitude space and hill-climbs toward the calmest setting. It changes one setting, waits, then checks whether crying or heart rate improved; if a change made things worse it steps back and tries the other axis, repeating until the baby reaches rest.